OpenAI's hilarious new patent diagrams have 'HBM stacked up like rice cakes'

I wouldn't claim to be an AI datacentre expert—good ol' fashioned PC gaming circuitry, that's my bread and butter—but I, along with everyone else and their collective brothers, know that those servers stack memory like nobody's watching. That's the reason we're living through a veritable RAMpocalypse, after all. So I can certainly laugh along with the various bewildered posts on X responding to OpenAI's latest patent.

The chip architecture patent [PDF], published on April 2, 2026, is for "a system of high bandwidth memory (HBM) chiplets and compute chiplets [which] includes embedded logic bridges that extend communication distances from the HBM chiplets to other chiplets beyond the ~6 mm limit imposed by the JEDEC standard."

The funny part, though, is the batch of incredibly simple diagrams that cram a whole bunch of memory alongside a compute chiplet. It screams 'you've heard of memory, but have you heard of more memory?' Which just about sums up the AI industry, I'd say.

The patent covers expanding the number of memory stacks beyond the normal limits by using those those fast "embedded logic bridges."

One patent analyst says on X that it's "HBM stacked up like rice cakes." And Citrini research analyst Jukan asks "What the hell is this thing?"

Putting a patent on essentially 'more memory' seems wild to me, but I admit I am oversimplifying. I'm sure there will be plenty of technical hoops to jump through to get those HBM stacks communicating with each other effectively at such a distance from the central compute chiplet. Thank God there are some detailed diagrams to help us out.

Again, I kid, there are other more specific diagrams in there. Just let me have my fun. If these companies are set on continuing to gobble up our precious DRAM, we're at least entitled to the occasional laugh at their expense, are we not?